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IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES IDT74FCT3932-100
IDT74FCT32932-100 3.3V LOW SKEW PLL-BASED ADVANCE INFORMATION CMOS CLOCK DRIVER
Integrated Device Technology, Inc.
FEATURES:
* * * * * 0.5 MICRON CMOS Technology Guaranteed low skew 16 programmable frequency configurations 17 3-state outputs: 24 mA FCT3932 8 mA FCT32932 Output configuration: BANK1: 4 outputs BANK2: 8 outputs BANK3: 5 outputs Dedicated feedback output (Q_FB) Maximum output frequency: 100MHz VCC = 3.3V 0.3V Inputs can be driven from 3.3V or 5V components Available in 48 SSOP, TSSOP packages Suited to SDRAM applications
* * * * * *
DESCRIPTION:
The FCT3932 uses phase-lock loop technology to lock the frequency and phase of the feedback to the input reference clock. It provides a large number of low skew outputs that are configurable in 16 different modes using the CNTRL 1-4 inputs. A dedicated output, Q_FB, is provided to supply the PLL feedback and it should be connected to the FEEDBACK input. Q_FB is located adjacent to FEEDBACK to minimize the delay in the feedback path. In order to offset any delay in the output path from the FCT3932 output to a receiving device,
feedback path delay should be made to match this output path delay. The PLL consists of the phase/frequency detector, charge pump, loop filter and VCO. The FCT3932 requires no external loop filter components. The FCT3932 provides 17 outputs grouped in 3 banks with individual 3-state control and an additional dedicated feedback output with no disable. Connecting Q_FB to FEEDBACK ensures uninterrupted PLL operation when all outputs are disabled. Individual bank 3-state allows users to disable unused outputs in order to limit power dissipation or minimize switching noise. It also allows users to shut down outputs in low power modes while maintaining phase lock. The FCT3932 provides a LOCK pin that goes high when the device is phase-locked. The user can bypass the PLL for testability purposes by deasserting PLL_EN. In this "test" mode, the input frequency is not limited to the specified range. The FCT3932 provides an asynchronous reset input, which resets all outputs. This initializes all internal registers so that outputs start up in a known state.
RST,
APPLICATIONS:
SDRAM DIMM Clock, Caches, high speed microprocessors, motherboard clock distribution to DIMMs.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
LOCK Charge Pump & Loop Filter Voltage Controlled Oscillator
REF_IN
Phase/Freq. Detector
PLL_EN
0 Mux
1
OE1 OE2 OE3
Q41-4 (BANK 1) Q81-8 (BANK 2) Q51-5 (BANK 3)
C O N T R O L CNTRL1-4
Q_FB
RST
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
NOVEMBER 1996
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DSC-3267/2
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IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
VCC Q55 CNTRL1 GND CNTRL2 CNTRL3 VCC CNTRL4 Q_FB FEEDBACK GND REF_IN AVCC NC AGND GND OE1 OE2 OE3 RST GND PLL_EN LOCK VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP TSSOP TOP VIEW
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ABSOLUTE MAXIMUM RATINGS(1)
48 47 46 45 44 43 42 41 40 39 38 Q54 Q53 GND Q52 Q51 VCC Q44 Q43 GND Q42 Q41 VCC VCC Q88 Q87 GND Q86 Q85 VCC Q84 Q83 GND Q82 Q81
Description Max. VTERM(2) Terminal Voltage with Respect to -0.5 to +4.6 GND (3) Terminal Voltage with Respect to -0.5 to +7.0 VTERM GND VTERM(4) Terminal Voltage with Respect to -0.5 to VCC GND + 0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +60
Symbol
Unit V V V C mA
SO48-1 37 SO48-2 36 35 34 33 32 31 30 29 28 27 26 25
3267 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.2 3.7 Max. 5.0 8.0 Unit pF pF
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NOTE: 1. This parameter is measured at characterization but not tested.
*NC = No connect
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IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Name REF_IN FEEDBACK Q41-4 Q81-8 Q51-5 I/O I I O O O I I O I I O Reference clock input. Feedback input to phase detector. BANK1 clock outputs. BANK2 clock outputs. BANK3 clock outputs. Output enable controls for BANKS 1, 2 and 3 (Active LOW). Control lines to select output configuration (see table). Dedicated PLL feedback output. Asynchronous reset (Active LOW). Disables phase-lock for low frequency testing (Refer to functional block diagram). PLL "LOCK" indicator (HIGH when PLL is locked).
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Description
OE1-3
CNTRL1-4 Q_FB
RST
PLL_EN LOCK
OUTPUT FREQUENCY CONFIGURATION AND INPUT FREQUENCY RANGE TABLE
MODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CNTRL 4321 00 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 10 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1 Q_FEEDBACK F (divide-by-1) F (divide-by-1) F (divide-by-1) F (divide-by-1) F (divide-by-1) F (divide-by-3) F (divide-by-3) F (divide-by-3) F (divide-by-2) F (divide-by-2) F (divide-by-2) F (divide-by-2) F (divide-by-2) F (divide-by-4) F (divide-by-4) F (divide-by-4) Q_BANK1 (4 outputs) Q_BANK2 (8 outputs) F F F F/2 F/3 3F F 3F 2F F F F F/2 2F 2F 2F Q_BANK3 (5 outputs) F F/2 F F/2 F F 3F 3F 2F 2F F F/2 F 4F 2F F FIN Range 50-100MHz 50-100MHz 50-100MHz 50-100MHz 50-100MHz 16.7-33.3MHz 16.7-33.3MHz 16.7-33.3MHz 25-50MHz 25-50MHz 25-50MHz 25-50MHz 25-50MHz 12.5-25MHz 12.5-25MHz 12.5-25MHz
3267 tbl 04
F F
F F F 3F 3F 3F 2F 2F 2F 2F 2F 4F 4F 4F
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IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to 70C, VCC = 3.3V 0.3V
Symbol VIH VIL II H II L IOZH IOZL VIK IODH IODL ICCL ICCH ICCZ Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Input LOW Level (Input and I/O pins) Input HIGH Current (Input pins) Input LOW Current (Input pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Quiescent Power Supply Current VCC = Max. VCC = Max. VI = 5.5V VI = GND VO = VCC VO = GND VCC = Min., IIN = -18mA VCC = 3.3V, VIN = VIH or VIL, VO = VCC = 3.3V, VIN = VIH or VIL, VO = VCC = Max., VIN = GND or VCC 1.5V (3) 1.5V (3) -- -- -- -- -- -36 50 -- -- -- -- -- -0.7 -75 75 -- 6 1 1 1 1 -1.2 V mA mA mA A A Guaranteed Logic LOW Level Test Conditions(1) Guaranteed Logic HIGH Level Min. 2.0 2.0 -0.5 Typ.(2) -- -- -- Max. 5.5 VCC+0.5 0.8 V Unit V
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TYPE 1 DRIVER - FCT3932
Symbol VOH Parameter Output HIGH Voltage VCC = Min. Test Conditions(1) IOH = -0.1mA IOH = -8mA IOL = 0.1mA IOL = 16mA IOL = 24mA Min. Typ.(2) VCC-0.2 -- 2.2 (4) -- -- -- 2.4 -- 0.2 0.3 Max. -- -- 0.2 0.4 0.5
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Unit V
VIN = VIH or VIL VCC = 3.0V VIN = VIH or VIL VCC = Min. VIN = VIH or VIL
VOL
Output LOW Voltage
V
TYPE 2 DRIVER - FCT32932
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = Min. IOH = -0.1mA VIN = VIH or VIL VCC = 3.0V VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -8mA IOL = 0.05mA IOL = 4mA IOL = 8mA 2.4 (4) -- -- -- 3.0 -- 0.2 0.3 -- 0.2 0.4 0.5
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Min. Typ.(2) VCC-0.2 --
Max. --
Unit V
VOL
Output LOW Voltage
V
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. VOH = VCC -0.6V at rated current.
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IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol tRISE/FALL Frequency Parameter Rise/Fall Times REF_IN input (0.8V to 2.0V) Input Frequency REF_IN input Modes 0, 1, 2, 3, 4 Modes 5, 6, 7 Modes 8, 9, 10, 11, 12 Modes 13, 14, 15 Duty Cycle Input Duty Cycle, REF_IN input Min. -- 50 16.7 25 12.5 25 Max. 3.0 100 33.3 50 25 75 %
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Unit ns MHz
OUTPUT FREQUENCY SPECIFICATIONS
Mode 0, 1, 2, 3,4 Operating frequency 5, 6, 7 8, 9, 10, 11, 12 Operating frequency Operating frequency 13, 14, 15 Operating frequency Parameter F, F Outputs F/2 Outputs F/3 Outputs 3F Outputs F Outputs 2F Outputs F Outputs F/2 Outputs 4F Outputs 2F Outputs F Outputs Min. 50 25 16.7 50 16.7 50 25 12.5 50 25 12.5 Max. 100 50 33.3 100 33.3 100 50 25 100 50 25
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Unit MHz
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Total Power Supply Current (5,6) VCC = Max. Test Conditions(1) VIN = VCC -0.6V(3) F = 50Mhz Min. -- -- Typ.(2) 2.0 72 Max. 30 Unit A A/ MHz/ bit mA
IC
VCC = Max. VIN = VCC All Outputs Open VIN = GND 50% Duty Cycle MODE 10 VCC = Max. PLL_EN = 1, LOCK = 1, MODE 10 REF_IN frequency = 50MHz. All outputs open
--
62
3267 tbl 08 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (f) + ILOAD ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) f = SYNC input frequency ILOAD = Dynamic Current due to load.
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IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(7)
Symbol tPD(3) REF_IN-Q_FB tRISE/FALL All Outputs tPW(3) tSKEWr(3,4) tSKEWf(3,4) tSKEWall(3,4) tLOCK (5) Output Duty Cycle Output to Output Skew (All outputs at same frequency rising edge) Output to Output Skew (All outputs at same frequency falling edge) Output to Output Skew (All outputs, rising edge any frequency) Time required to acquire Phase-Lock from time REF_IN input signal is received Output Enable Time OEx (LOW-to-HIGH) to Q Output Disable Time OEx (HIGH-to-LOW) to Q Parameter Propagation Delay (REF_IN input to Q outputs) Rise/Fall Time (between 0.8 and 2.0V) FCT3932 FCT32932 Condition(1) No Load CL = 20pF for FCT3932 CL = 10pF for FCT32932 Min.(2) -0.5 0.5 0.5 45 -- -- -- 1 Max. +0.5 1.5 2.0 55 500 500 1.0 10 % ps ps ns ms Unit ns ns
tPZH tPZL tPHZ tPLZ
3.0 3.0
8.0 8.0
ns ns
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GENERAL AC SPECIFICATION NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested. 3. These specifications are guaranteed but not production tested. 4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage. 5. With VCC fully powered-on and Q_FB properly connected to the FEEDBACK pin. 6. The tPD spec gives the limits of the phase offset between the REF_IN input and the Q_FB output. 7. The AC specifications are only guaranteed with the decoupling scheme shown in figure 2.
tPD = 0.5ns
REF_IN input
Offset
Feedback Output
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IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
Board VCC Plane 10F
(1)
(43) (37) 0.1F
(7) 0.1F (13) FCT3932
(36)
0.1F (24) 0.1F
(30) 0.1F
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Figure 2. Recommended Decoupling for the FCT3932/FCT32932 NOTES: 1. Figure 2 shows a decoupling scheme which will be effective in most FCT3932 applications. The following guidelines should be followed for stable, jitterfree operation: a. All decoupling capacitors should be connected as close to the package as possible. (Preferably at the device pins). b. The 10F and 0.1F bypass capacitors provide protection from power supply and ground plane transients.
STANDARD LOAD (USED WHEN SPECIFIED)
500 50pF
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IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUIT
VCC
ENABLE/DISABLE TEST CIRCUIT
6.0V VCC Open 500 VIN Pulse Generator
RT CL
VIN Pulse Generator D.U.T.
VOUT
GND
VOUT D.U.T. CL RT 500
PROPAGATION DELAY, OUTPUT SKEW
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REF_IN INPUT
tPD
3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL
Q_FB tSKEWr tSKEWf
Qxx tSKEWr tSKEWf
Qyy tSKEWall tSKEWf
VOH 1.5V VOL VOH 1.5V VOL tSKEWr
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Qzz
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT t PZL OUTPUT NORMALLY SWITCH LOW CLOSED t PZH OUTPUT SWITCH NORMALLY OPEN HIGH 3.5V 1.5V 0.3V t PHZ 0.3V 1.5V 0V 0V
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SWITCH POSITION
3V 1.5V t PLZ 0V 3.5V V OL V OH
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch 6V
DISABLE
GND Open
3267 lnk 14 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: tF 2.5ns; tR 2.5ns
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IDT74FCT3932-100, IDT74FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX FCT IDT XX Temp. Range Device Type X Speed X Package
PV PA 100
Small Shrink Outline Package (SO48-1) Thin Shrink Small Outline Package (SO48-2) 50 - 100Mhz
3932 3.3V Low skew PLL-based 32932 CMOS clock driver 74 0C to +70C
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